JSSC 2010第4期RF & Wireless90nmVCOHigh-Speed Link

A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS Kangmin Hu, Student Member , IEEE, Tao Jiang , Student Member , IEEE , Jingguang Wang, Frank O’Mahony, Member , IEEE, and Patrick

本文提出了一种基于注入锁定环形振荡器的四通道6.4-7.2 Gb/s串行链路接收器，具有高能效和宽调谐范围。

6.4-7.2 Gb/s数据速率，BER<10^-12，0.6 mW/Gb/s能效

注入锁定环形振荡器串行链路接收器相位去偏低功耗设计CMOS工艺

▸创新点1：使用注入锁定环形振荡器（ILRO）实现相位去偏，这是一种方法创新，通过ILRO生成多个时钟相位，实现大于一个单位间隔（UI）的相位偏移，消除了传统架构中的相位旋转和插值需求，显著简化了时钟恢复电路。

▸创新点2：低功耗线性均衡器设计，属于电路创新，通过优化均衡器的线性度和功耗，在1.2V 90nm CMOS工艺下实现了高效的信号补偿，支持6.4-7.2 Gb/s的数据速率，同时保持低功耗。

▸创新点3：低电压摆幅全局时钟分配，是一种系统创新，通过降低时钟信号的电压摆幅，减少了时钟分配网络的功耗，同时通过ILRO耦合实现了稳定的时钟同步，测量显示功耗效率为0.6 mW/Gb/s。

▸创新点4：四通道偏移消除量化器设计，属于电路创新，用于1:4解复用，通过消除偏移提高了接收器的信号完整性，支持高达8.0 Gb/s的数据速率，并通过14 cm PCB传输实现BER<10^-12。

Abstract

This paper describes a quad-lane, 6.4–7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpo- lation required in conventional architectures. Each receiver, opti- mized for power efﬁciency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an in- jection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4–7.2 Gb/s data rate with BER 10 /49/50across 14 cm of PCB, and also an 8.0 Gb/s data rate through 4 cm of PCB. Designed in a 1.2 V , 90 nm CMOS process, the ILRO achieves a wide tuning range from 1.6–2.6 GHz. The total area of each receiver is 0.0174 mm /50, resulting in a mea- sured power efﬁciency of 0.6 mW/Gb/s.