JSSC 2010第4期Data Converters0.13μmSAR ADCNeural Network Accelerator

A 10-bit 50-MSs SAR ADC With a Monotonic Capacitor Switching Procedure Chun-Chen

提出一种低功耗10位50MS/s SAR ADC，采用单调电容切换程序。

1.2V, 50 MS/s, SNDR 57.0 dB, 0.826 mW, FOM 29 fJ/conversion-step

SAR ADC单调电容切换低功耗比较器共模电压

▸创新点1：单调电容切换程序（方法创新）。该技术通过优化电容切换顺序，显著降低了平均切换能量和总电容，分别减少了81%和50%，从而提高了ADC的能效。

▸创新点2：改进的比较器（电路创新）。通过优化比较器设计，减少了输入共模电压变化引起的信号依赖偏移，提高了ADC的精度和稳定性。

▸创新点3：输入共模电压逐渐收敛到地（系统创新）。该技术使输入共模电压逐步接近地电位，减少了系统噪声和干扰，进一步提升了ADC的信噪比（SNDR）至57.0 dB。

▸创新点4：低功耗设计（系统创新）。在1.2V电源电压下，ADC仅消耗0.826mW，实现了29 fJ/conversion-step的优异能效比（FOM），适用于低功耗应用场景。

Abstract

This paper presents a low-power 10-bit 50-MS/s suc- cessive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the