JSSC 2010第4期Power Management0.13μmTDCNeural Network Accelerator

A 12-Bit V ernier Ring Time-to-Digital Converter in 013 22m CMOS Technology

提出了一种12位Vernier环形时间数字转换器，用于数字锁相环，具有8ps时间分辨率和低功耗。

0.13μm CMOS, 1.5V, 15MSPS, 7.5mW

数字锁相环频率合成时间测量相位测量时间数字转换器

▸Vernier延迟单元和仲裁器环形排列

▸预逻辑单元测量正负相位误差

▸同时实现大检测范围和高时间分辨率

Abstract

Fellow, IEEE, and Richard C. Jaeger , Life Fellow, IEEE Abstract—A 12-bit V ernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel V ernier ring TDC places the V ernier delay cells and arbiters in a ring format and reuses them for the measure- ment of the input time interval. The proposed TDC thus achieves large detectable range, ﬁne time resolution, small die size and low power consumption simultaneously. A pre-log