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JSSC 2010第4期Wireline I/O40nm

A 43 GBs Mobile Memory Interface With Power-Efficient Bandwidth Scaling Brian Lei

本文提出了一种4.3 GB/s的移动内存接口,通过快速低功耗状态转换实现高效带宽调节。
40nm低功耗CMOS技术, 3.3 mW/Gb/s能效, 4.3 GB/s带宽
低功耗内存接口带宽调节时钟暂停差分信号
全局同步时钟暂停实现快速功耗状态转换
半比特率时钟同步通信
低摆幅差分信号驱动提升信号完整性和能效
Abstract
IEEE, John Poulton , Senior Member , IEEE, Y ohan Frans, Member , IEEE, Simon Li, John Wilson, Michael Bucher , Member , IEEE, Andrew M. Fuller, John Eyles, Marko Aleksic´, Member , IEEE, Trey Greer, and Nhat M. Nguyen Abstract—This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock