← 返回 JSSC 论文列表JSSC 2010第4期Data Converters90nmFlash ADC
A Background Self-Calibrated 6b 27 GSs ADC With Cascade-Calibrated Folding-Inter
一款采用背景自校准技术的6位2.7 GS/s ADC，通过级联校准折叠插值架构降低功耗50%
90nm CMOS, 1.0V, 2.7GS/s, 50mW, FOM 0.47pJ/conversion-step
背景自校准折叠插值ADC低功耗设计高速ADC数字补偿
▸数字背景自校准架构补偿器件失配和环境漂移
▸双通道ADC架构与数字平滑技术实现多GHz操作
▸级联校准折叠插值架构降低50%模拟功耗
Abstract
We have developed a 6b 2.7 GS/s folding ADC with
on-chip background self-calibration in 90 nm CMOS technology.
The ADC achieves high-speed operation of 2.7 GS/s at low power
consumption of 50 mW from a 1.0 V power supply and the figure
of merit (FOM) is 0.47 pJ/conversion-step. The key technique is
a digital background self-calibration architecture which compen-
sates for the large mismatch of small devices in the ADC and also
corrects the ADC characteristics degradation during operation
due to t