A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture Y uji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Norihito Kato, Tetsuya Matsumoto, and Michio Y otsuyanagi, Member , IEEE

Abstract

We have developed a 6b 2.7 GS/s folding ADC with on-chip background self-calibration in 90 nm CMOS technology. The ADC achieves high-speed operation of 2.7 GS/s at low power consumption of 50 mW from a 1.0 V power supply and the figure of merit (FOM) is 0.47 pJ/conversion-step. The key technique is a digital background self-calibration architecture which compen- sates for the large mismatch of small devices in the ADC and also corrects the ADC characteristics degradation during operation due to the drift of environmental factors such as temperature. This background calibration technique suited for multi-GHz operation is realized by two-channel ADC architecture and digital smoothing technique, which uses averaging of two comparator offsets and reconfiguration of reference connection. T o minimize the power dissipation, a cascade-calibrated folding-interpolating architec- ture has been developed. It reduces the overall analog power of our design by 50%, compared with a conventional architecture which applies calibration only to preamplifiers. By utilizing these low-power techniques, we have successfully developed a low-power ADC with all functions including the background self-calibration control circuit.