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A Fractional-N PLL for Multiband 086 GHz Communications Using Binary-Weighted DA
设计了一种紧凑、低功耗且容忍全局失配的0.8-6 GHz分数N锁相环，用于多频带通信。
0.8-6 GHz频率范围，量化噪声降低25dB，带内杂散降低20dB（仿真）/8dB（实测）
分数N锁相环多频带频率合成器ΔΣ调制数字-模拟转换二进制加权数字-模拟微分器
▸采用二阶二进制加权数字/模拟微分器（DAD）实现二阶失配整形，量化噪声降低25dB
▸提出三阶偏移频率ΔΣ调制器，带内杂散降低20dB（仿真）和8dB（实际电路）
▸相比动态元件匹配（DEM）方案，具有更小的布线面积和更低的功耗
Abstract
lator
Heng-Yu Jian, Member , IEEE, Zhiwei Xu , Member , IEEE, Yi-Cheng Wu , Member , IEEE, and
Mau-Chung Frank Chang, Fellow, IEEE
Abstract—A compact, low power and global-mismatch-tolerant
0.8–6 GHz fractional-
PLL is designed to cover IEEE 802.11abg,
PCS/DCS and cellular bands. Two new techniques are proposed to
cancel the in-band quantization noise and fractional spurs. Firstly,
a second order binary-weighted digital/analog differentiator
(DAD) is utilized to enable the second order mismatch