← 返回 JSSC 论文列表JSSC 2010第4期Data Converters0.18μmPipeline ADCDelta-Sigma ADC
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-SigmaPipelined ADC Omid Rajaee Stud
设计了一种混合型ΔΣ/流水线ADC，结合噪声整形与分布式量化，降低功耗并提高分辨率。
0.18μm CMOS, 80MHz时钟, 8倍过采样率(5MHz带宽), 79dB动态范围, 75.4dB SNDR
混合型ADCΔΣ调制器流水线ADC噪声整形CMOS
▸结合ΔΣ调制器的噪声整形与流水线ADC的分布式量化
▸利用流水线量化的延迟增强噪声整形
▸显著降低积分器的增益、摆幅和压摆率要求
Abstract
A hybrid delta-sigma/pipelined modulator is pre-
sented in this paper. The proposed modulator takes advantage
of the high resolution and distributed pipelined quantization,
and combines it with the noise shaping property of a delta-sigma
modulator. As a result, gain, swing, and slew requirements of
the integrators are significantly reduced. The modulator also
makes use of the latency in the pipelined quantization to enhance
noise shaping. These advantages lead to less power dissipation,
increased