← 返回 JSSC 论文列表JSSC 2010第5期Clocking & PLLs65nm
A 127 GHz All-Digital Spread Spectrum Clock GeneratorSynthesizer in 65 nm CMOS D
65nm CMOS工艺下实现的全数字扩频时钟发生器，最高频率1.27GHz，电磁干扰峰值降低20.5dB。
65nm CMOS, 1.27GHz, 44mW@1.27GHz, 20.5dB EMI降低(750MHz, 6%调制深度)
扩频时钟发生器电磁干扰抑制数字控制延迟线全数字设计CMOS工艺
▸全数字标准单元设计流程实现
▸采用数字控制延迟线实现任意调制波形
▸实时测量电路跟踪工艺电压温度变化
Abstract
erto Romani, Nicola Petra , Member , IEEE,
Antonio Giuseppe Maria Strollo , Senior Member , IEEE, and Claudio Parrella
Abstract—Spread spectrum clocking is an effective solution to
reduce the electromagnetic interference produced by digital chips,
using a clock signal with a frequency that is intentionally swept
(frequency modulated) within a certain frequency range, with a
predefined modulation profile.
We present the implementation of an all-digital spread spec-
trum clock generator. The circuit