← 返回 JSSC 论文列表JSSC 2010第5期Data Converters0.18μmPipeline ADCCharge Pump
A Low-Power Capacitive Charge Pump Based Pipelined ADC
提出一种基于电容电荷泵的低功耗流水线ADC，无需高功耗运放即可实现高线性度。
1.8V, 0.18μm CMOS, 50MS/s, 58.2dB SNDR (9.4 ENOB), 66dB SFDR, 3.9mW (模拟)/6mW (数字)
ADC电荷泵CMOS低功耗流水线
▸创新点1：使用电容电荷泵替代传统运放，显著降低功耗，同时实现10位线性度，无需高功耗运放。
▸创新点2：采用源极跟随器和数字校准技术，提升ADC线性度，确保在50 MS/s采样率下达到58.2 dB的SNDR。
▸创新点3：无需显式共模反馈电路，简化电路设计，减少功耗和面积开销，适用于低功耗应用场景。
▸创新点4：在1.8 V、0.18 μm CMOS工艺下实现3.9 mW的低功耗设计，适用于移动设备等对功耗敏感的应用。
Abstract
bstract—A low-power pipelined ADC topology is presented
which uses capacitive charge pumps, source-followers, and dig-
ital calibration to eliminate the need for power-hungry opamps
to achieve good linearity in a pipelined ADC. The differential
charge pump technique achieves
10-bit linearity, and does not
require an explicit common-mode-feedback circuit. The ADC was
designed to operate at 50 MS/s in a 1.8 V , 0.18
m CMOS process,
where measured results show the peak SNDR and SFDR of the
ADC to b