← 返回 JSSC 论文列表JSSC 2010第5期Clocking & PLLs0.13μm
A Low THD Low Power High Output-Swing Time-Mode-Based Tunable Oscillator Via Dig
提出一种低THD、低功耗、高输出摆幅的时间模式可调谐振荡器设计方法。
0.13μm CMOS, 1.2V, 10MHz, 72dB THD, 228mV差分输出摆幅, 3.37mA电流消耗
低THD时间模式可调谐振荡器数字谐波消除高输出摆幅
▸采用数字谐波消除块抑制低频谐波
▸使用无源线性滤波器抑制高频谐波
▸无需传统高Q值带通滤波器，实现纯数字解决方案
Abstract
An architectural solution for designing and imple-
menting low THD oscillators is presented. A digital harmonic-can-
cellation-block is used to suppress the low-frequency harmonics
while a passive, inherently linear , filter is used to suppress the
high-frequency ones. The proposed technique eliminates the
need for typical high-Q BPF to suppress the harmonics. Thus,
eradicates the effect of increasing device nonlinearities in the
nanometric technologies by having pure digital solution. In ad-
dit