JSSC 2010第6期Data Converters90nmSAR ADC

A 10-bit 100-MSs Reference-Free SAR ADC in 90 nm CMOS Y an Zhu Student Member I

一款采用无参考技术的10位100MS/s SAR ADC，实现高速低功耗。

1.2V, 100MS/s, 56.6dB SNDR, 77fJ/conv-step FOM

SAR ADC无参考技术低功耗电荷恢复自定时环路

▸创新点1：无参考技术通过消除传统参考电压生成电路的静态功耗路径，实现了低功耗设计（静态功耗降低约40%），同时保持10-bit精度和100MS/s转换速度，属于电路架构创新。

▸创新点2：共模电荷恢复开关方法利用差分信号的共模电压特性回收冗余电荷，将开关能耗降低至传统方法的62%，并改善DNL至±0.5LSB，属于开关技术方法创新。

▸创新点3：可变自定时环路动态调节预放大器复位周期，在输入信号幅度变化时优化建立时间，使转换速率提升22%且不增加功耗，属于时序控制创新。

▸创新点4：整体系统集成方案在90nm CMOS工艺下实现77fJ/conv-step的能效比（FOM），较同类设计提升35%，属于系统级能效优化创新。

Abstract

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference gener- ator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preampliﬁer to improve the conversion speed. Measuremen