JSSC 2010第6期RF & Wireless65nmCDR

A 5-Gbs ADC-Based Feed-Forward CDR in 65 nm CMOS Oleksiy Tyshchenko Ali Sheikhol

一篇关于在65纳米CMOS工艺中实现5Gbs ADC-Based Feed-Forward CDR的论文

5 Gb/s, 178.4 mW, 0.51 mm²

ADCCDRCMOS时钟恢复数据恢复

▸创新点1：ADC-based CDR技术采用双倍数据率的盲采样方法，通过高速模数转换器直接处理接收信号，显著提高了时钟和数据恢复的精度与效率，适用于5 Gb/s高速通信场景。

▸创新点2：盲采样接收信号技术无需预先知道数据相位，通过自适应算法实时调整采样点，降低了系统复杂度并提升了鲁棒性，特别适合多速率通信环境。

▸创新点3：直接估计零交叉点位置的方法通过数字信号处理技术快速定位信号跳变点，减少了传统CDR中的模拟电路依赖，实现了178.4 mW低功耗和0.51 mm²小面积。

▸创新点4：65 nm CMOS工艺下的系统集成优化，结合ADC与数字处理模块的协同设计，在5 Gb/s速率下实现了高性能与低功耗的平衡，为高速SerDes提供了新解决方案。

Abstract

This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We successfully conﬁrmed the operation of the proposed CDR architecture at 5 Gb/s. The receiver is implemented in 65 nm CMOS, occupies 0.51 mm /50, and consumes 178.4 mW at 5 Gb/s.