A Differential Data-Aware Power-Supplied D50AP 8T SRAM Cell With Expanded WriteR

Abstract

Due to global and local process variations, on-chip SRAM suffers failures at a low supply voltage (VDD). This study proposes a differential data-aware power-supplied D /50AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, the proposed 8T cell applies differential data-aware-supplied voltages to its cross-cou- pled inverters to increase both stability margins for w