JSSC 2010第6期Clocking & PLLs0.18μm CMOSPLLNeural Network Accelerator

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

提出一种动态相位误差补偿技术，用于快速锁相的PLL设计。

5GHz, 11mA@1.8V, 114.3dBc/Hz@1MHz, <-70dBc@10MHz

锁相环快速锁定动态补偿相位误差电荷泵

▸创新点1：动态监测并补偿PFD输入的相位误差，通过实时监控相位误差的极性和大小，确保在锁定过程中始终保持较小的相位误差，显著减少了PLL的锁定时间。

▸创新点2：通过动态改变分频比实现粗调，利用分频比的动态调整对相位误差进行粗补偿，进一步优化了频率捕获过程，提高了PLL的整体锁定速度。

▸创新点3：采用辅助电荷泵加速频率捕获，在快速锁定模式下，辅助电荷泵向环路滤波器提供额外电流，显著加快了频率捕获速度，提升了PLL的动态性能。

▸创新点4：在TSMC 0.18-μm CMOS工艺下实现了5-GHz PLL设计，实测锁定时间显著优于传统带宽切换方法，相位噪声在1-MHz偏移处为-114.3 dBc/Hz，参考杂散在10-MHz偏移处低于-70 dBc，展示了优异的性能指标。

Abstract

This paper presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratio of the frequency divider. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process, thereby reducing th