← 返回 JSSC 论文列表JSSC 2010第6期Clocking & PLLs0.18μmDelta-Sigma ADC
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in
一款六阶200 MHz中频带通Σ-Δ调制器，10 MHz带宽下峰值SNDR达68.4 dB。
200MHz中心频率, 10MHz带宽, 68.4dB SNDR, 160mW功耗
Σ-Δ调制器带通滤波器中频ADC连续时间调制器过采样ADC
▸采用三阶线性化运放实现200 MHz下50 dB增益的主动RC环路滤波器
▸提出PVT变化校准技术，通过注入辅助音优化噪声传递函数
▸在0.18μm CMOS工艺下实现高IF应用
Abstract
vas, Praveena Kode, Jose Silva-Martinez , Fellow, IEEE, and Sebastian Hoyos
Abstract—This paper presents a sixth-order bandpass /6/1
modulator with 10 MHz bandwidth and 200 MHz center fre-
quency suitable for high-IF applications. The
/52modulator
employs an 800 MHz clock frequency and uses an active RC
loop filter implemented with three-stage linearized operational
amplifiers achieving more than 50 dB gain at 200 MHz. Fur-
thermore, a calibration technique is proposed to compensate for
process–v