Abstract
, Fellow, IEEE, Bram Nauta , Fellow, IEEE,
Fabio Sebastiano, Student Member , IEEE , Kofi A. A. Makinwa , Senior Member , IEEE , and
Lucien J. Breems , Senior Member , IEEE
Abstract—The design of a duty-cycled PLL (DCPLL) capable
of burst mode operation is presented. The proposed DCPLL is a
moderately accurate low-power high-frequency synthesizer suit-
able for use in nodes for wireless sensor networks (WSN). Thanks
to a dual loop configuration, the PLL ’s total frequency error, once
in lock, is l