Abstract
E, Ashoke Ravi , Member , IEEE, Luis Cuellar , Member , IEEE,
Stefano Pellerano, Member , IEEE, Parmoon Seddighrad, Ismael Lomeli, and Y orgos Palaskas , Member , IEEE
Abstract—A technique is presented for implementing time-in-
terleaved pipelined high-speed digital /1/6modulators using stan-
dard cells and the tools for digital design (synthesis and automatic
place-and-route). Time interleaving allows clocking the standard
cell blocks at submultiples of the final sampling rate. The proposed
tech