← 返回 JSSC 论文列表JSSC 2010第8期RF & Wireless65nmPLLVCO
A 24-GHz Low-Power All-Digital Phase-Locked Loop Liangge Xu Student Member IEEE
本文介绍了一种用于2.4GHz ISM频段的低功耗全数字锁相环。
65nm CMOS, 0.24 mm², 12 mW, 120 dBc/Hz @1MHz
全数字锁相环数字控制振荡器频率合成ISM频段低功耗
▸创新点1：采用数字控制LC振荡器（DCO），通过全数字化设计替代传统模拟VCO，显著提升频率合成的灵活性和工艺适应性，同时降低功耗和面积。
▸创新点2：在参考信号路径中引入短延迟线技术，使时间数字转换器（TDC）核心以低占空比工作，平均功耗降低约95%，显著优化系统能效。
▸创新点3：提出自适应增益校准的两点调制方案，支持直接频率调制，通过动态校准增益误差提升调制精度，适用于高带宽无线通信场景。
▸创新点4：采用高速可变相位累加器拓扑结构，精确计数RF输出的完整周期，提升相位分辨率，实测集成相位噪声低至1.7° rms。
Abstract
, Member , IEEE, and
Jussi Ryynänen, Member , IEEE
Abstract—This paper presents an all-digital phase-locked loop
(ADPLL) for the 2.4-GHz ISM band frequency synthesis. The
ADPLL is built around a digitally controlled LC oscillator. In the
feedback path, a high-speed topology is employed for the variable
phase accumulator to count full cycles of the RF output. A simple
technique based on a short delay line in the reference signal path
allows the time-to-digital converter core to operate at a low