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JSSC 2010第8期Data Converters130nmSAR ADCDelta-Sigma ADC

A 31 mW Continuous-Time 16Modulator With 5-Bit Successive Approximation Quantize

本文提出了一种基于5位逐次逼近量化器的多位连续时间ΔΣ调制器，旨在降低量化器功耗和面积。
130nm CMOS, 1.2V, 62dB动态范围, 1.92MHz带宽, 31mW功耗
连续时间ΔΣ调制器逐次逼近量化器低功耗动态范围CMOS
▸创新点1：使用逐次逼近量化器替代闪存量化器，显著降低量化器功耗和面积，提升系统效率。
▸创新点2：有效补偿量化器延迟，确保系统稳定性，避免因延迟导致的性能下降。
▸创新点3：低功耗设计，采用130 nm CMOS技术，仅消耗3.1 mW，实现62 dB动态范围。
▸创新点4：结合动态元素匹配技术，优化多比特量化器的线性度，提高整体信号质量。
Abstract
Arash Mehrabi , Member , IEEE, Omid Oliaei , Senior Member , IEEE, and Frederic Carrez Abstract—In this paper , we present a multibit continuous-time delta-sigma modulator based on a 5-bit successive approximation quantizer. The use of successive approximation, instead of flash, is driven by the desire to reduce the quantizer power and area. The quantizer delay is effectively compensated to ensure system stability. The modulator is implemented in a 130 nm CMOS tech- nology and achieves 62 dB of d