An Embedded All-Digital Circuit to Measure PLL Response

Abstract

EE, Richard J. DeSantis, and Gerry R. Talbot, Member , IEEE Abstract—We present an all-digital measurement circuit that en- ables wafer-level test and characterization of phase-locked loop (PLL) response. Through modifications only in the PLL feedback divider state machine, this technique facilitates accurate estima- tion of PLL frequency-domain closed-loop bandwidth and gain peaking by respectively measuring the time-domain crossover time and maximum overshoot of phase error to a self-induced ph