← 返回 JSSC 论文列表JSSC 2010第9期Data Converters90-nmDACClock Generation
A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS Hong Chang Y eoh, Student Member , IEEE , Jae-Hun Jung , Student Member , IEEE , Y un-Hwan Jung, Student Member , IEEE
本文提出了一种基于混合设计的低功耗直接数字频率合成器，最大工作频率为1.3 GHz。
90-nm CMOS, 1.2-V digital supply, 2.5-V analog supply, 1.3 GHz, 350 mW
直接数字频率合成器数字模拟转换器流水线累加器分段非线性DAC低功耗
▸混合设计扩展了传统非线性DAC的分辨率
▸通过线性DAC增加线性斜率分量
▸11位组合DAC实现最小52 dBc的无杂散动态范围
Abstract
Jung , Student Member , IEEE ,
Y un-Hwan Jung, Student Member , IEEE, and Kwang-Hyun Baek , Senior Member , IEEE
Abstract—This paper presents a low-power direct digital fre-
quency synthesizer (DDFS) based on a hybrid design with a max-
imum operating frequency of 1.3 GHz. The proposed hybrid de-
sign is capable of extending the resolution of traditional nonlinear
digital-to-analog converter (DAC)-based DDFS by adding a linear
slope component to the approximated sine wave produced from a
nonline