← 返回 JSSC 论文列表JSSC 2010第9期Clocking & PLLs0.18μm CMOSDelta-Sigma ADC
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With
一款采用七相400MHz时钟方案的5阶连续时间低通Σ-Δ调制器，具有25MHz带宽和67.7dB峰值SNDR。
25MHz带宽, 67.7dB SNDR, 48mW功耗, 1.8V电源, 2.6mm²面积
连续时间Σ-Δ调制器宽带无线接收脉冲宽度调制DAC注入锁定分频器两步量化器
▸七相400MHz时钟控制的时间处理技术
▸3位两步量化器与单元素DAC结合的脉冲宽度调制反馈
▸片上压控振荡器与注入锁定分频器的低抖动时钟生成
Abstract
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Cho-Ying Lu, Student Member , IEEE , Marvin Onabajo , Member , IEEE, V enkata Gadde,
Y ung-Chung Lo, Student Member , IEEE , Hsien-Pu Chen , Student Member , IEEE ,
Vijayaramalingam Periasamy, Student Member , IEEE, and Jose Silva-Martinez , Fellow, IEEE
Abstract—This paper introduces a continuous-time low-pass
sigma-delta modulator operating with a seven-phase 400 MHz
clocking scheme to control time-based processing in the 3-bit
two-step quantizer and main digital-to-analog convert