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JSSC 2010第9期Other0.35μm

A Floating-Gate-Based Field-Programmable Analog Array

提出一种基于浮栅晶体管的现场可编程模拟阵列,具有高性能和集成度。
0.35μm CMOS, 57MHz带宽, 5MHz低通滤波器
浮栅晶体管现场可编程模拟阵列高性能集成度路由结构
使用浮栅晶体管实现可编程互连和电路元件
消除SRAM存储配置位的需求
改进路由结构以减少带宽损失
Abstract
hubha Ramakrishnan, Csaba Petre, Student Member, IEEE , Scott Koziol, Faik Baskaya , Member, IEEE , Christopher M. Twigg, Member, IEEE, and Paul Hasler , Senior Member, IEEE Abstract—A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 3m m /50 in 0.35- m CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and pro- grammable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The progra