← 返回 JSSC 论文列表JSSC 2010第9期Clocking & PLLs0.18μm CMOSPLLVCO
Spur Reduction Techniques for Phase-Locked Loops
本文提出了一种利用子采样相位检测器和振幅控制电荷泵的PLL参考杂散抑制技术。
2.21 GHz, -80 dBc参考杂散, 3.8 mW功耗, -121 dBc/Hz相位噪声, 0.3 ps抖动
锁相环参考杂散子采样相位检测器低功耗低相位噪声
▸使用子采样相位检测器（SSPD）
▸振幅控制电荷泵减少失配影响
▸采用虚拟采样器和隔离缓冲器降低VCO采样杂散
Abstract
ric A. M. Klumperink , Senior Member , IEEE, Gerard Socci , Member , IEEE,
Mounir Bohsali, Member , IEEE, and Bram Nauta , Fellow, IEEE
Abstract—This paper presents phase-locked loop (PLL) refer-
ence-spur reduction design techniques exploiting a sub-sampling
phase detector (SSPD) (which is also referred to as a sampling
phase detector). The VCO is sampled by the reference clock
without using a frequency divider and an amplitude controlled
charge pump is used which is inherently insensitive to m