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A 26 mW 6 bit 22 GSs Fully Dynamic Pipeline ADC in 40 nm Digital CMOS Bob V erbr
40纳米数字CMOS工艺下实现的26mW 6位22GS/s全动态流水线ADC
2.2 GS/s, 6位分辨率, 31.6 dB SNDR, 2 GHz ERBW, 2.6 mW功耗, 0.03 mm²面积
模数转换器流水线ADC动态放大器阈值校准高速低功耗
▸采用1位折叠级和流水线二进制搜索子ADC结构
▸利用动态非线性放大器降低功耗
▸通过阈值校准校正放大器和比较器的不完美
Abstract
r , IEEE, Maarten Kuijk , Member , IEEE,
Piet Wambacq, Member , IEEE, and Geert V an der Plas , Member , IEEE
Abstract—A 2.2 GS/s 4
-interleaved 6b ADC in 40 nm digital
CMOS is presented. Each ADC slice consists of a 1b folding stage
followed by a pipelined binary-search sub-ADC using dynamic
nonlinear amplifiers for low power consumption and high speed.
The folding stage samples the input, removes its common-mode
component and rectifies the differential voltage. The pipelined
binary-search sub-A