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A 3 Watt 398446 Gbs Dual-Mode SFI52 SerDes Chip Set in 65 nm CMOS Nikola Nedovic
一款65nm CMOS工艺的双模SFI5.2兼容SerDes芯片组，功耗3W，支持40Gb/s光收发器。
65nm CMOS, 3W, 21.5–22.3 Gb/s DQPSK, 39.8–44.6 Gb/s NRZ
SerDesCMOS光收发器低功耗双模
▸创新点1：双模DQPSK/NRZ支持 - 该芯片通过创新的调制技术实现了对DQPSK和NRZ两种模式的支持，能够在21.5–22.3 Gb/s DQPSK或39.8–44.6 Gb/s NRZ之间灵活切换，显著提升了系统的适应性和应用范围。
▸创新点2：低功耗设计 - 采用65 nm CMOS工艺和标准单元设计，总功耗仅为3 W，比商用BiCMOS SFI5 40 Gb/s SerDes ICs降低了75%，在高速数据传输中实现了显著的能效优化。
▸创新点3：标准单元CMOS实现 - 通过内部解复用至16个2.5 Gb/s通道，所有逻辑和可测试性功能均采用标准单元CMOS实现，降低了制造成本并提高了设计灵活性，同时芯片面积仅为4 mm²。
▸创新点4：高集成度封装技术 - 芯片采用倒装焊（flip-chip）技术封装到四边扁平封装（quad flat-pack）中，进一步提升了系统的紧凑性和可靠性，适用于高密度光学转发器应用。
Abstract
A Dual-mode 2
21.5–22.3 Gb/s DQPSK or
1
39.8–44.6 Gb/s NRZ to 4
9.95–11.2 Gb/s SFI5.2-compliant
two-chip SerDes for a family of 40 Gb/s optical transponders has
been fabricated in 65 nm 12-metal CMOS. By demultiplexing to
16
2.5 Gb/s internally, all logic and testability functions could
be implemented in standard-cell CMOS, resulting in total power
consumption of 3 W, 75% lower than commercial BiCMOS SFI5
40 Gb/s SerDes ICs. Chip area is 4
4 mm, and the ICs are
flip-chip mounted into a quad fla