← 返回 JSSC 论文列表JSSC 2010第10期Data Converters0.35μmPipeline ADCTime-Interleaved ADC
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Tim
一种四通道时间交织ADC，采用数字校准技术，提升信号质量。
11-bit, 160-MS/s, 0.35-μm CMOS
时间交织ADC数字校准双采样通道失配信号质量
▸数字校准技术：通过数字校准算法有效校正通道间失配误差和双采样引入的存储误差，将信噪失真比从45 dB提升至62 dB，显著提高ADC的动态性能（系统创新）
▸双采样技术：采用双采样结构在0.35μm CMOS工艺下实现160-MS/s采样率，通过时间交织技术提升吞吐量，同时利用校准消除由此产生的记忆效应（电路创新）
▸通道间失配校正：提出针对四通道时间交织ADC的专用校准方案，将无杂散动态范围从47 dB改善至79 dB，解决了多通道同步精度问题（方法创新）
▸混合信号设计优化：结合模拟前端双采样与数字后端校准的混合架构，在保持低功耗的同时实现11位精度，突破传统折衷限制（系统级创新）
Abstract
An 11-bit 160-MS/s four-channel time-interleaved
double-sampled pipelined ADC implemented in a 0.35-
m CMOS
process is described. Digital calibration is used to correct mis-
match errors between channels as well as the memory errors that
arise from the use of double sampling. The signal-to-noise-and-dis-
tortion ratio is improved from 45 to 62 dB after calibration with
an 8.7-MHz input. The spurious-free dynamic range is increased
from 47 dB to 79 dB.