JSSC 2010第10期Other90nm

A Low-Loss 5070 GHz SPDT Switch in 90 nm CMOS

90纳米CMOS工艺实现的50-70 GHz超低损耗SPDT开关，插入损耗最低1.5 dB。

插入损耗1.5-2.0 dB@50-70 GHz, 隔离度>25 dB, P1dB 13.5 dBm, IIP3 22.5 dBm@60 GHz

SPDT开关毫米波CMOS工艺低损耗50-70 GHz

▸采用/52传输线与并联电感输出匹配网络

▸实现50-70 GHz超宽频带低损耗

▸芯片面积仅0.5×0.55 mm²可进一步优化

Abstract

ract—This paper presents an ultra-low-loss 50–70 GHz single-pole double-throw (SPDT) switch built using a standard 90 nm CMOS process. The switch is based on /52transmission lines with shunt inductors at the output matching network. The SPDT switch results in a measured insertion loss of 1.5–1.6 dB at 53–60 GHz and 2.0 dB at 50–70 GHz. The measured isolation is 25 dB, and the output port-to-port isolation is 27 dB at 50–70 GHz. The measured P1dB is 13.5 dBm with a corresponding IIP3 of 22.5 dB