Abstract
, Koichi Nose , Member , IEEE, Y oshihiro Nakagawa,
Koichiro Noguchi, Y asuhiro Morita, Member , IEEE, Masamoto Tago, Masayuki Mizuno , Member , IEEE, and
Tadahiro Kuroda, Fellow, IEEE
Abstract—A small-size inductive-coupling dc voltage trans-
ceiver for highly-parallel wafer-level testing is experimentally
demonstrated in 90-nm CMOS technology, which can reduce the
total cost of a low-price IC by 18%. In order to carry out dc tests,
the proposed transceiver outputs dc voltage to the die-under-t