Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation

Abstract

Recent publications have shown that clock jitter can improve timing margin through the compensation effect between the clock cycle and the datapath delay under the influence of res- onant supply noise. This paper presents a comprehensive study of this beneficial clock-data compensation effect including an anal- ysis of its dependency on various design parameters and a new phase-shifted clock buffer design that can enhance the effect. Mea- surement result from a 1.2 V , 65 nm test chip shows an 8–2