50–250 MHz /1/6DLL for Clock Synchronization San-Jeow Cheng, Lin Qiu

Abstract

A /1/6 DLL targeted for clock synchronization has been proposed. Unlike other existing /1/6 DLL designs, the pro- posed DLL makes use of the /1/6 dithering in the feedback path rather than at the input, which eliminates the need of additional multi-phase generator , and hence simplifies the architecture and improves the jitter performance. It also employs a second order adaptive filter to achieve dynamic loop bandwidth control for different operating frequencies as well as a unique antiharmonic detector to avoid false locking. Clock synchronization is achieved in two steps. During the coarse tuning step, the delay edge from DLL that closely matched to the incoming clock is first deter- mined. In subsequent fine tuning step, a successive approximation method is then employed to quickly shift the selected delay edge to achieve synchronization with the incoming clock. Fabricated in 0.35 m CMOS technology, the /1/6 DLL core can operate from 50 to 250 MHz with a delay step resolution of 15 ps and occupy only 0.4 mm /50. It draws about 6.9 mA from 3 V supply at 200 MHz and exhibits an rms jitter of 2.1 ps.