← 返回 JSSC 论文列表JSSC 2010第11期Clocking & PLLs0.35μmDLLNeural Network Accelerator
50250 MHz 16DLL for Clock Synchronization San-Jeow Cheng Lin Qiu Yuanjin Zheng
提出一种用于时钟同步的50250 MHz 16DLL，简化架构并提升抖动性能。
0.35μm CMOS, 3V, 50-250MHz, 15ps延迟分辨率, 2.1ps rms抖动
时钟同步16 DLL抖动性能自适应滤波器抗谐波检测
▸反馈路径使用16 dithering
▸二阶自适应滤波器实现动态带宽控制
▸独特抗谐波检测器避免误锁
Abstract
A /1/6 DLL targeted for clock synchronization has
been proposed. Unlike other existing /1/6 DLL designs, the pro-
posed DLL makes use of the /1/6 dithering in the feedback path
rather than at the input, which eliminates the need of additional
multi-phase generator , and hence simplifies the architecture and
improves the jitter performance. It also employs a second order
adaptive filter to achieve dynamic loop bandwidth control for
different operating frequencies as well as a unique antiharmonic
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