JSSC 2010第11期RF & Wireless65nm

A2 25-Gbs Receiver With 25 DMUX for 100-Gbs Ethernet Ke-Chung Wu and Jri Lee Me

65nm CMOS技术实现的25Gbps接收器，支持100Gb以太网。

65nm CMOS, 1.2V, 510mW, 20-mV输入灵敏度

100Gb以太网时钟数据恢复解复用器限幅放大器抖动容限

▸新型调节机制减少限幅放大器的增益和带宽变化

▸集成低功耗全速率CDR和高速2:5 DMUX电路

▸双通道实现四通道操作

Abstract

r for 100-Gb Ethernet (100 GbE) has been implemented in 65-nm CMOS technology. A new regu- lation mechanism is applied to the limiting ampliﬁer to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX cir- cuit are integrated. Although only two channels are implemented, this receiver provides exactly the same operation as a four-channel one while dealing with independent channels. The prototype achieves bit error rate