JSSC 2010第11期Data Converters90nm

A CMOS 6-mW 10-bit 100-MSs Two-Step ADC Y ung-Hui Chung Student Member IEEE and

采用90nm CMOS工艺的10位100MS/s两步式ADC，功耗6mW，采用开环放大器和数字校准技术。

90nm CMOS, 1V, 100MS/s, 6mW, 58.2dB SNR, 75dB SFDR, 9.34 ENOB

两步式ADCCMOS低功耗数字校准开环放大器

▸创新点1：采用锁存型比较器（Latch-Type Comparators）进行信号数字化，显著降低功耗。该方法通过减少动态功耗和缩短比较时间，实现了在100-MS/s高速采样下的6-mW低功耗表现，属于电路级创新。

▸创新点2：使用开环放大器（Open-Loop Amplifier）进行残差放大，避免了传统闭环放大器的稳定性问题，同时优化了速度和功耗。这一设计在90 nm CMOS工艺下实现了10-bit精度，属于架构级创新。

▸创新点3：通过数字背景校准（Digital Background Calibration）技术提升比较器偏移和残差放大器的增益精度与线性度。该创新使ADC的SNR达到58.2 dB，SFDR达75 dB，ENOB达9.34 bits，属于系统级创新。

▸创新点4：结合上述技术，整体ADC实现100 fJ/conv.-step的优异能效比（FOM），在1 V电源电压下兼顾高速与低功耗，属于系统级性能突破。

Abstract

A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. T o reduce power consumption, the ADC uses latch-type comparators for signal digitalization and an open-loop ampliﬁer for residue ampliﬁcation. The accuracy of the comparators is improved by offset calibration. The gain accuracy and the linearity of the residue ampliﬁer are enhanced by digital background calibration. The ADC consumes 6 mW from a 1 V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respec- tively. Mea