← 返回 JSSC 论文列表JSSC 2010第11期Clocking & PLLs40nm
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous V oltage Scaling in DVFS
一种采用预测延迟调整方案的低功耗宽范围时钟同步器
40nm CMOS, 0.8-1.55V, 100MHz-1GHz, 偏斜<6.8%时钟周期, 0.48mA@1.1V/100MHz
时钟同步器动态电压频率调节低功耗宽范围预测延迟调整
▸创新点1：短范围偏斜测量技术（方法创新） - 通过优化测量范围，显著降低了时钟同步器的面积和功耗，同时保持了高精度的同步性能。
▸创新点2：预测延迟调整(PDA)方案（电路创新） - 采用预测性延迟调整机制，有效减少了时钟偏斜，使其在宽电压和频率范围内保持稳定，偏斜率低于6.8%。
▸创新点3：面积减少77%（系统创新） - 通过优化电路设计和布局，大幅缩小了芯片面积，在40-nm CMOS工艺下实现仅为51mm²的面积。
▸创新点4：低功耗设计（电路创新） - 在1.1V、100MHz工作条件下，电流消耗仅为0.48mA，显著降低了功耗，适用于低功耗应用场景。
Abstract
A wide-range voltage-and-frequency clock synchro- nizer (WRCS) for maintaining synchronization during dynamic voltage-and-frequency scaling was developed. The key feature of the WRCS is short-range skew measurement based on a predic- tive-delay-adjustment (PDA) scheme. The short-range skew mea- surement results in reduction of the area of the WRCS by 77%, that is, the area of the fabricated WRCS in a 40-nm CMOS process is only /53 /54/53 /49/48 /51mm/50. In the case of large voltage variation (0.8–1.55 V) and wide frequency range (100 MHz–1 GHz), mea- sured skew is suppressed to the lowest percentage yet reported, namely, less than 6.8% of clock period. Moreover, current con- sumption of the WRCS is only 0.48 mA under 1.1-V 100-MHz operation.