The SpeedPower Trade-Off in the Design of CMOS True-Single-Phase-Clock Dividers

Abstract

In this work, we introduce a true-single-phase-clock (TSPC) divider synthesis technique that is based on the general TSPC logic family. According to this unified technique, various types of TSPC dividers are compared in terms of the speed–power trade-off. The newly proposed RE-2 type has shown better balance between speed and power performance than other types. The mea- surement results of a prototype design in a 65 nm LP CMOS tech- nology show that the maximal input frequencies can be 19 GHz and