JSSC 2010第12期RF & Wireless45nm

A4 7 10 Gbs 14 mWGbs Parallel Interface in 45 nm CMOS Frank OMahony Member IEEE

45nm CMOS工艺下实现的低功耗高密度并行芯片间接口

45nm CMOS, 10Gb/s, 660mW, 1.4mW/Gb/s, 3.2mm²

芯片间接口低功耗并行传输CMOS时钟优化

▸创新点1：时钟信号优化降低功耗（系统创新）。通过分摊时钟信号和最小化时钟信号的范围，显著降低了整体功耗，具体表现为接口总功耗仅为660 mW，效率达到1.4 mW/Gb/s。

▸创新点2：低摆幅发射器与高灵敏度接收器配对（电路创新）。采用低摆幅发射器驱动与高灵敏度接收器采样器的组合，有效降低了信号传输的功耗，同时保持了高数据速率（10 Gb/s）和低误码率（BER < 10^-12）。

▸创新点3：片上传输线布线减少面积（方法创新）。通过创新的片上传输线布线技术，将有效硅面积压缩了64%，相对于传统的C4凸点布局，显著提升了集成密度，最终仅占用3.2 mm²的活跃硅面积。

▸创新点4：快速电源管理与唤醒机制（系统创新）。接收器在待机模式下功耗可降低93%，并通过集成唤醒计时器实现53 ns内所有通道可靠返回激活模式，显著提升了能效和响应速度。

Abstract

A4 7 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing trans- mitter driver with a sensitive receiver sampler. The active silicon area is compressed by 64% relative to the C4 bumps using on-chip transmission line routing. A dense, top-side package connector and b