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A 123-mW 125-Gbs Complete Transceiver in 65-nm CMOS Process Koji Fukuda Member
基于65nm CMOS工艺的12.3mW 12.5Gb/s完整收发器设计
12.3mW, 12.5Gb/s, 0.98mW/(Gb/s), BER≤10^-12
低功耗串行链路收发器CMOS时钟数据恢复
▸采用低摆幅电压模式驱动器和脉冲电流增强技术
▸使用LC谐振时钟分布与分布式片上电感
▸符号速率相位检测器和可变延迟相位旋转PLL
Abstract
mber , IEEE, Ryo Nemoto, Eiichi Suzuki,
Noboru Masuda, Takashi Takemoto, Fumio Y uki, and Tatsuya Saito , Member , IEEE
Abstract—A 12.3-mW 12.5-Gb/s complete transceiver based
on the 65-nm standard digital CMOS process was developed.
The chip includes a clock-and-data-recovery (CDR) device,
a multiplexer/demultiplexer (MUX/DEMUX), and a global
clock-distribution network. To reduce power consumption, a
low-swing voltage-mode driver with pulse-current boosting and
an LC resonant-clock distribution