A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR

Abstract

This paper describes a 16-bit analog-to-digital converter designed in a complementary SiGe BiCMOS SOI process. The high-performance complementary BJTs lead to a switched-current approach to the signal processing. Although it uses a fairly traditional four-stage pipeline architecture, sev- eral techniques are incorporated to achieve 16 bits of distortion performance at a sample rate of up to 160 MHz. For improved high input frequency linearity we describe a track and hold with a sampling instant modulation scheme. For stability of the cur- rent-mode DAC over signal swing and temperature we describe a scheme to increase the output impedance of the first sub-DAC. At a sample clock frequency of 122 MHz, prototype silicon exhibits a spurious-free dynamic range of 100 dBc through the first two Nyquist zones and a signal-to noise ratio of 77 dB. With a 160 MHz sampling clock, the measured SFDR is better than 90 dBc and the SNR is better than 74.5 dB. The ADC dissipates 1.6 W from 5 V and 3.3 V supplies.