← 返回 JSSC 论文列表JSSC 2010第12期Data Converters0.18μmPipeline ADCNeural Network Accelerator
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration Ahmed M. A. Ali, Member , IEEE, Andrew (Andy) Morgan, Christopher Dillon, Greg Patterson, Scott Puckett
一款16位250MS/s的IF采样流水线ADC，采用新型线性化技术和背景校准技术。
0.18μm BiCMOS, 1.8V/3V, 250MS/s, SNDR 76.5dB, SFDR >95dB@100MHz
模数转换器背景校准输入缓冲器中频采样流水线
▸新型线性化技术提高输入缓冲器失真性能5-10dB并降低70%功耗
▸求和节点采样(SNS)背景校准技术校正残留放大器增益误差
▸无采样保持放大器(SHA-less)设计
Abstract
Christopher Dillon, Greg Patterson, Scott Puckett,
Paritosh Bhoraskar, Member , IEEE, Huseyin Dinc, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore,
Jeff Bray, Carroll Speir, and Robert Sneed
Abstract—This paper describes a 16-bit 250 MS/s ADC fabri-
cated on a 0.18
m BiCMOS process. The ADC has an integrated
input buffer with a new linearization technique that improves its
distortion by 5–10 dB and lowers its power consumption by 70%
relative to the state of the art. It demonstrate