JSSC 2010第12期Clocking & PLLs0.18μm CMOSPLLNeural Network Accelerator

A 1 GHz ADPLL With a 125 ps Minimum-Resolution Sub-Exponent TDC in 018 22m CMOS

一篇关于采用自适应分辨率TDC的全数字PLL设计的IEEE JSSC论文。

最小分辨率1.25 ps，总转换范围2.5 ns，最大工作频率250 MHz，60 MHz时功耗1.8 mW

全数字PLL时间数字转换器时间放大器自校准CMOS

▸自适应缩放分辨率的时间数字转换器(TDC)

▸级联两个时间放大器以提高效率

▸基于复制的自校准方案改善线性度

Abstract

ark , Member , IEEE, and Jae-Y oon Sim, Member , IEEE Abstract—An all-digital PLL for wireline applications is de- signed with a sub-exponent TDC which adaptively scales its resolution according to input time difference. By cascading 2 time ampliﬁers, the TDC efﬁciently generates the exponent-only information for fractional time difference. To improve linearity in a wide input range, a replica-based self-calibration scheme is applied to the time ampliﬁer. The TDC, implemented in a 0.18 m CMOS, s