← 返回 JSSC 论文列表JSSC 2010第12期Power Management90nmTDCClock Generation
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter Takashi Tokairin
一款采用时间窗口TDC技术的低相位噪声全数字锁相环频率合成器
105 dBc/Hz相位噪声, 8.1 mA功耗, 1.2V电源
全数字锁相环时间数字转换器低相位噪声CMOS频率合成器
▸创新点1：采用时间窗口TDC技术，通过单脉冲操作显著降低功耗，同时保持高精度时间测量，适用于低功耗无线通信系统。该技术在90nm CMOS工艺下实现，功耗仅为8.1mA。
▸创新点2：两步结构提高时间分辨率，结合逆变器和Vernier延迟时间量化器，有效降低相位噪声至-105 dBc/Hz（带内）和-115 dBc/Hz（带外），提升系统整体性能。
▸创新点3：单脉冲操作降低功耗，通过时间窗口操作优化TDC的工作模式，减少动态功耗，同时保持系统的高精度和稳定性，适用于高频（21-to-28 GHz）应用场景。
▸创新点4：数字密集型架构实现高可编程性和可扩展性，通过数字环路滤波器替代传统模拟滤波器，减少芯片面积（0.37 mm²），同时提升系统的抗噪声能力和鲁棒性。
Abstract
airin, Mitsuji Okada , Member , IEEE, Masaki Kitsunezuka, Tadashi Maeda , Member , IEEE, and
Muneo Fukaishi, Member , IEEE
Abstract—A 2.1-to-2.8-GHz low-power consumption all-digital
phase locked loop (ADPLL) with a time-windowed time-to-dig-
ital converter (TDC) is presented. The time-windowed TDC uses
a two-step structure with an inverter- and a V ernier-delay time-
quantizer to improve time resolution, which results in low phase
noise. Time-windowed operation is implemented in the TDC, in
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