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JSSC 2010第12期Power Management65nmTDC

A 35 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering a

本文提出了一种通过TDC抖动抑制分数杂散的全数字锁相环设计。
65nm CMOS, 1.2V, 3.5GHz
分数-N全数字锁相环抖动频率合成器时间数字转换器
TDC抖动方法抑制分数杂散
前馈抖动消除技术降低相位噪声
全数字校准算法确保PVT条件下的相位噪声消除
Abstract
, Colin Weltin-Wu, Daniele Baldi, Marco Cusmai, and Francesco Svelto , Member , IEEE Abstract—Nonlinearities in the time-to-digital converter (TDC) are a significant source of fractional spurs in a divider-less frac- tional-N ADPLL. Using an abstract model for the TDC, this paper presents a dithering method which is mathematically shown to suppress fractional tones, in conjunction with a feedforward dither cancellation technique which suppresses dither-induced phase noise. A mostly-digital calibr