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JSSC 2010第12期RF & Wireless65nmPLL

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

本文介绍了一种低功耗源同步链路接收器宏的设计,支持3.2-6.4 Gb/s的数据速率。
65nm CMOS, 6.4 Gbps, 635 mW (4.5 mW/Gbps)
高速串行链路时钟生成时钟和数据恢复源同步链路抖动
脉冲式CDR设计以节省功耗
时间抖动技术避免抖动容忍曲线缺口
可选择清理PLL或多相滤波器生成接收时钟
Abstract
ember , IEEE, Michael Ruegg , Member , IEEE, Fran Keyser, John Bergkvist, Daniel Dreps, Member , IEEE, Thomas Toifl , Senior Member , IEEE, and Martin Schmatz , Member , IEEE Abstract—This paper describes the design of a product-level low-power source-synchronous link receiver macro for data rates of 3.2–6.4 Gb/s. The receiver macro consists of 22 data channels plus one forwarded-clock channel, and supports both differential and ground termination. A pulsed CDR with programmable band- width is im