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JSSC 2010第12期Data Converters65nmDelta-Sigma ADC

A Mostly-Digital V ariable-Rate Continuous-Time Delta-Sigma Modulator ADC Gerry

一种主要基于数字电路的可重构连续时间ΔΣ调制器ADC
65nm LP CMOS, 8–17 mW, 0.5–1.15 GHz, 3.9–18 MHz, 67–78 dB SNDR
连续时间ΔΣ调制器ΔΣ ADCVCO ADC数字校准低功耗
▸数字背景校准技术：通过数字电路实现动态校准，显著降低传统模拟校准的复杂性和功耗，在65nm CMOS工艺中实现67-78dB的峰值SNDR（系统创新）
▸自消除抖动技术：采用新型数字信号处理算法消除VCO固有抖动，提升信噪比至78dB，无需外部低抖动时钟（方法创新）
▸全数字化架构创新：完全去除模拟积分器、反馈DAC和比较器，仅保留VCO作为唯一模拟模块，芯片面积缩小至0.07mm²（电路创新）
▸可重构带宽设计：通过数字控制实现3.9-18MHz带宽动态调节，支持0.5-1.15GHz可变采样率（系统级创新）
Abstract
r Member , IEEE Abstract—This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that con- sists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance per- formance. Unlike conventional delta-sigma modulators, it does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require