Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal

Abstract

Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution A/D converters in deep submicron CMOS processes. One possible implementation of Split-CLS is presented, which achieves very high effective gain, and combines the fast, high efficiency charging of a zero-crossing based circuit (ZCBC) with the high-accuracy, low power settling of a double-cascode telescopic opamp. A dynamic zero-crossing de- tector (ZCD) conserves power in the ZCBC by only creating high bandwidth in the ZCD near the zero-crossing instant. Measured results are presented from a pipelined A/D converter fabricated in 0.18 m CMOS. Using the Split-CLS structure, an opamp with 300 mV output swing is used to produce a pipeline stage output swing of 1.4 V. The proof-of-concept test chip achieves 68.3 dB SNDR (11.1b ENOB) and 76.3 dB SFDR while sampling at 20 MHz, and consumes 17.2 mW at 1.8 V supply.