← 返回 JSSC 论文列表JSSC 2011第1期Memory32nmSRAM
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for L
32纳米高k金属栅SRAM采用自适应动态稳定性增强技术
32nm CMOS, 3.4Mb SRAM阵列, 传感器面积开销0.02%, 功耗开销2%
SRAM高k金属栅工艺变异字线欠驱动Vccmin优化
▸自适应动态SRAM字线欠驱动方案
▸基于位单元的传感器动态优化WLUD强度
▸降低SRAM Vccmin 130mV同时提高频率良率9%
Abstract
Eric Karl , Member , IEEE, Uddalak Bhattacharya , Member , IEEE,
Fatih Hamzaoglu, Member , IEEE, Henry Nho, Yong-Gee Ng, Yih Wang , Member , IEEE, and
Kevin Zhang, Senior Member , IEEE
Abstract—SRAM bitcell design margin continues to shrink due
to random and systematic process variation in scaled technologies
and conventional SRAM faces a challenge in realizing the power
and density benefits of technology scaling. Smart and adaptive
assist circuits can improve design margins while satisfying SRA