A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada

Abstract

In this paper we introduce a 14-core application processor for multimedia mobile applications, implemented in 40 nm, with a 222 mW H.264 full high-definition (full-HD) video engine, a 124 mW 40 M-polygons/s 3D/2D graphics engine, and a video/audio multiprocessor for various Codecs and image processing. The application processor has 25 power domains to achieve coarse-grain power gating for adjusting to the required performance of wide range of multimedia applications. The simple on-chip power switch circuits perform less than 1 s switching while reducing rush current. Furthermore, the Stacked Chip SoC (SCS) technology enables rewiring to the DRAM chip during assembly/packaging phase using a wire with 10 m minimum pitch on Re-Distribution Layer (RDL) using electroplating. The peak memory bandwidth is 10.6 GB/s with an x512b SCS-DRAM interface, and the power consumption of this interface is 3.9 mW at 2.4 GB/s workload.