A 45 nm Resilient Microprocessor Core for Dynamic V ariation Tolerance Keith A. Bowman, Member , IEEE, James W . Tschanz, Member , IEEE, Shih-Lien L. Lu , Senior Member , IEEE, Paolo A. Aseron, Muhammad M. Khellah , Member , IEEE

Abstract

A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock fre- quency /40/70/67/76/75/41guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detec- tion sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the /70/67/76/75guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage /40/86/67/67/41measurements. Both error-detection designs inter- face with error-recovery techniques, enabling the detection and correction of timing errors from