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A 45 nm Resilient Microprocessor Core for Dynamic V ariation Tolerance
45nm微处理器核心通过两种容错设计动态适应参数变化，提升吞吐和能效。
45nm CMOS, 动态参数变化容错, 提升吞吐和能效
微处理器动态容错错误检测时序恢复能效优化
▸嵌入错误检测时序电路（EDS）减少动态变化保护带
▸可调谐复制电路（TRC）实现非侵入式动态时序错误检测
▸结合错误恢复技术检测和纠正时序错误
Abstract
A 45 nm microprocessor core integrates resilient
error-detection and recovery circuits to mitigate the clock fre-
quency
/40/70/67/76/75/41guardbands for dynamic parameter variations
to improve throughput and energy efficiency. The core supports
two distinct error-detection designs, allowing a direct comparison
of the relative trade-offs. The first design embeds error-detec-
tion sequential (EDS) circuits in critical paths to detect late
timing transitions. In addition to reducing the
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