← 返回 JSSC 论文列表JSSC 2011第1期Digital Circuits65nm
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correctio
一种采用时序错误检测与纠正技术的低功耗32位ARM处理器
65nm工艺, 724MHz最差情况STA签核, 1GHz下52%功耗降低
时序错误检测动态电压频率调整ARM处理器功耗优化PVT变化容忍
▸动态时序错误检测与纠正技术(Razor)
▸运行时自适应电压频率调整方案
▸带粘性错误历史位的Razor单元设计
Abstract
PVT V ariation
David Bull, Shidhartha Das , Member , IEEE, Karthik Shivashankar, Ganesh S. Dasika , Student Member , IEEE,
Krisztian Flautner, Member , IEEE, and David Blaauw , Senior Member , IEEE
Abstract—Razor is a hybrid technique for dynamic detection
and correction of timing errors. A combination of error detecting
circuits and micro-architectural recovery mechanisms creates
a system that is robust in the face of timing errors, and can be
tuned to an efficient operating point by dynamicall