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JSSC 2011第1期Digital Circuits65nm

Within-Die V ariation-Aware Dynamic- V oltage-Frequency-Scaling With Optimal Cor

针对80核处理器提出基于芯片内变异的动态电压频率优化方案,提升能效6%-35%。
65nm CMOS, 80-core, 6%-35% energy efficiency improvement
芯片内变异动态电压频率调节能效优化80核处理器网络芯片
基于芯片内核心间性能变异的最优动态电压频率调节(DVFCS)
动态线程跳跃方案提升性能5%-10%或能效20%-60%
对比SVMF、MVSF和MVMF设计的能效优化效果
Abstract
TeraFLOPS Processor Saurabh Dighe, Member , IEEE, Sriram R. V angal, Member , IEEE, Paolo Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman , Member , IEEE, Jason Howard , Member , IEEE, James Tschanz , Member , IEEE, V asantha Erraguntla, Member , IEEE, Nitin Borkar, Vivek K. De , Senior Member , IEEE , and Shekhar Borkar, Fellow, IEEE Abstract—In this paper , we present measured within-die core-to-core Fmax and leakage variation data for an 80-core processor in 65 nm CMOS and 1) populate a para